The Mate 60 and the limits of sanctions
In August 2023 Huawei put a phone on sale carrying a 7-nanometer-class ("7-nm") processor, fabbed domestically, in defiance of export controls designed to cripple China's domestic chipmaking. Two extreme interpretations of that event emerged. One saw the Mate 60 Pro as proof the sanctions had failed and the frontier was cracked. The other read it as a stunt: ruinous yields on old machines, unsustainable at any scale. Both stories ran, sometimes in the same publication, and both still run: depending on the week, China is either 20 years behind in chipmaking or one secret lab away from parity.
Their actual progress is public and out in the open: patents, national standards, peer-reviewed papers, equipment roadmaps, quarterly reports. The chip was real and it was no one-off: SMIC has printed successors to it every year since, its third-generation 7-nm node built the same way.1 But all of them are printed with 193 nm light on ASML's older deep-ultraviolet (DUV) machines, using a sequence of deposition and etch steps to reach pitches the light itself cannot resolve. The machine that can print those nodes in one pass, the extreme ultraviolet (EUV) machine, is the one tool China can neither buy nor yet build. China is not caught up, nor is it 20 years behind across the board; it is blocked at the EUV machine, and progressing on every other part of chipmaking.
Moore's Law meets Rayleigh's Law
For 60 years chips got faster, cheaper and more efficient the same way: by cramming more transistors into the same square millimeter of silicon. Doing that continuously is Moore's Law, and the price of computing fell for as long as it held. For most of those 60 years the count was set by one quantity: the smallest feature the printing machine could resolve in a single exposure, which is called the critical dimension. Every halving of the critical dimension translates to four times the density of transistors.
The physics is described by one equation, borrowed from Lord Rayleigh's 19th century work on telescope resolution:
Shorter light, wider lens, better tricks – three ways to print smaller, and every lithography improvement ever made has come from moving one of those three.
By 2007 all three moves were spent. k₁ stood a shade under 0.28, near the floor. The argon-fluoride light had been at 193 nm since the turn of the century. The final gain came from the lens: a layer of water between lens and wafer, which raised the aperture to 1.35. Multiply it out and the critical dimension sat at about 40 nm. That was the smallest feature a single exposure could print in 2007. It improved once more, to 38 nm in 2008, and then not again for 11 years.2
Unlike the light source, the density of transistors per square millimeter kept rising through those 12 years. Fabs printed a pattern, shifted the wafer and printed again, building one circuit layer out of two exposures, then four; they redesigned the cells to win area lithography no longer gave. Between Intel's 45-nm node and TSMC's N7, density rose roughly 27-fold while the single-exposure limit stood all but still.3 What it cost was masks, tool time, alignment tolerance and yield.
During those 12 years, the node names tracked neither density nor smallest feature. Six of them – "45" down to "7" – shipped against that all-but-frozen limit, and they have since moved on to describing new nodes with "ångströms" (tenths of a nanometer) in the name, while the features stay an order of magnitude larger.
Then in 2019, after two decades of painstaking engineering, at moments nearly out of funding, ASML finally moved the wavelength (λ) from 193 nm all the way down to 13.5 nm: a 14-fold cut. No prior change of light had brought even a two-fold improvement. A single exposure could suddenly print a 13 nm feature. Every leading-edge node introduced at TSMC and Samsung since, and every future node on the global roadmap out another decade, is built on this single ASML machine, the Twinscan EUV; from TSMC's N5 in 2020, the frontier could no longer be printed economically any other way.
The unassailable moat of ASML
This was an all-out assault on the boundaries of physics, and the light had to be violent by design. A generator fires 50,000 droplets of molten tin per second, each a third the width of a human hair; a 30 kW carbon-dioxide laser strikes each droplet twice, the first pulse flattening it, the second detonating it into a 220,000 °C plasma (some 40 times the temperature at the surface of the sun). That tin plasma radiates light at 13.5 nm until the next droplet arrives.4
Nothing transmits 13.5 nm light: not glass, not air, not any material a lens could be made from. At that wavelength every substance absorbs it. So there are no lenses in an EUV scanner: the beam travels in vacuum, and every optical surface it meets is a mirror.
Another problem arises: nothing in the natural world wants to reflect EUV light either. A mirror has to be coaxed into existence by stacking 40 to 50 pairs of molybdenum and silicon layers, each a few nanometers thick. One layer alone reflects almost nothing; spaced exactly right, the faint reflections resonate and add up instead of cancelling out. And an EUV mirror is curved, not flat. Light strikes every point at a different angle, so the layer spacing must be graded point by point across the whole meter-scale optic to keep the reflection tuned everywhere at once.
The coating is only half the mirror. Beneath it, the surface itself is shaped to picometer accuracy, in a loop: measure, correct, measure again. The loop can only fix what it can see, so a mirror can be made no more accurate than the interferometer that checks it. In optics of this class, the measuring instrument is the real frontier. Mirrors that can do the work a Twinscan requires have exactly one supplier in the world: Zeiss.
Zeiss, despite being the frontier of optics, can still only make mirrors 70% reflective, and the beam needs 11 of them to get from plasma to wafer. About 2% of the light ever arrives for printing.5
None of it was supposed to work. The droplet generator, the graded mirrors, the interferometers behind the mirrors, the vacuum, the dose arriving 50,000 times a second: each sits at the limit of its own discipline, and the machine needs all of them at once, around the clock, in a fab that expects uptime. 30 years of physicists, chemists and engineers on three continents solved one impossible problem after another and then made the result repeatable, shippable and serviceable. The EUV machine was a daring bet, and now having paid off, a testament to human ingenuity.
The Twinscan ships from Veldhoven, Netherlands. The foundational work was done by the EUV LLC, a consortium led by Intel, IBM, AMD, et al operating with Lawrence Livermore, Sandia and Lawrence Berkeley national laboratories. The research ran in America's public labs, and industry paid $250 million over three years for it. The largest private investment a Department of Energy research project had ever received. ASML joined in 1999 and acquired the last American maker of leading-edge scanners, SVG, in 2001. Nikon and Canon, who had taken the leading edge from the American pioneers a generation earlier, were on the outside; both built full-field EUV development tools, and neither ever announced an exit. Canon’s last public EUV work was in 2009, Nikon’s in 2011. They challenged, and lost.6 In 2012 Intel, TSMC and Samsung took a combined 23% stake in ASML (€3.85 billion) through its Customer Co-Investment Program, and funded a further €1.38 billion of its next-generation lithography research and development, rather than build an alternative because no single balance sheet would carry the bet.7 American laboratories did the research; American industry paid for it; a Dutch company owns the product; the three largest chipmakers on earth are its shareholders and its customers.
ASML is still improving the Twinscan. The source has gone from 1 W in 2010 to 250 W in the 2018 production tool, and in 2025 ASML demonstrated 1,000 W in a proof of concept: 100,000 tin droplets a second, three pulses each, with production tools targeted around 2030. The lens roadmap for numerical aperture runs from 0.33 to 0.55 to 0.75 across two decades, all on the same tin-mediated 13.5 nm light.8
The deeper we glimpse into a Twinscan, the safer its monopoly looks.
Reinventing the transistor beyond optics
Chip development out to 2038 is mapped by a research institute in Leuven, Belgium called imec, whose contributors span the supply chain from TSMC and Intel to the toolmakers like ASML and LAM. Exhibit 2 shows the latest published roadmap.
The transistor reinvents itself, the nanosheet giving way to the CFET, one device stacked on top of its complement; power delivery moves to the back of the wafer; standard cells shed tracks; the map's last column bonds two finished wafers face to face. The lens aperture opens up one notch (the 0.55 lens at "A14," fed by a new class of metal-oxide resists) and holds it for four consecutive nodes, until the final column hedges on a 0.75 lens that does not exist. The wavelength never moves.9 Most of the next phase of pushing the frontier up till 2038 is no longer about the EUV. And all of it besides the Twinscan is available for China to work on, too.
China against the imec roadmap
- Device stacking & bonding – Wafer-to-wafer hybrid bonding is the step vertical stacking depends on. YMTC has shipped it in NAND since 2021, is reported to have licensed patents to Samsung, and holds more hybrid-bonding patents than any other memory maker, behind only TSMC and Adeia in the field as a whole.10
- Materials (2D channels) – Beyond the 2038 horizon: atom-thick channel materials, long studied as silicon's successor. Chinese groups are among the field's most prolific publishers and have demonstrated wafer-scale growth: 12-inch MoS₂ wafers grown in batches at Peking University, and a 5,900-transistor microprocessor built entirely from MoS₂ at Fudan. The imec consortium still leads on 300 mm integration.11
- Patterning (the k₁ term) – Locked out of EUV, Chinese fabs became the heaviest users of the k₁ term. SiCarrier filed and received a patent in 2023 for a self-alignment process that removes the need for an EUV cut mask, describing it as a pattern solution for 5-nm-class back-end wiring on DUV tools.12
- Etch & deposition – AMEC and NAURA put China near the frontier as toolmakers rather than as fabs. AMEC's 5-nm etch tools were verified by TSMC back in 2018, and over 270 of its chambers now run in 5-nm-and-below lines worldwide; NAURA's furnaces fill SMIC's mature lines.13
- Power delivery (backside) – Optional on imec's map until the CFET arrives, then mandatory. China's work sits in the open research record; none of it has reached a production line.
- Advanced packaging (2.5D) – The real gap: 2.5D integration, TSMC's Chip-on-Wafer-on-Substrate (CoWoS), the platform under every serious AI accelerator. Domestic capacity is minimal and the equipment largely imported; China's four listed packaging houses announced over ¥27 billion of new capacity in the first half of 2026 alone.14 The tool side runs ahead of the capacity side: in packaging lithography, SMEE's spin-off AMIES claims roughly 90% of the domestic market and about a third of the global one.15
- EDA – Domestic flows serve the mature nodes; advanced-node sign-off still runs on Cadence, Synopsys and Siemens.
Every one of these is a lever the embargo left open, and the record shows all of them being worked at once. The gaps in the chart's lower half are the kind money, volume and iteration can close, because the knowledge behind them is distributed across a global supply chain rather than fused into one monopoly. Overlay China's public portfolio on Exhibit 2 – the stacking, the materials, the patterning, the backside power – and it is the same roadmap, lane for lane, filled everywhere but the light.
The τ Law
On 25 May 2026, at the IEEE International Symposium on Circuits and Systems in Shanghai, Huawei board member and president of its semiconductor business unit 何庭波 (He Tingbo), gave a keynote titled "New Semiconductor Path in Practice" where she proposed a successor to Moore's Law: 韬（τ）定律 (tāo dìnglǜ, Tau (τ) Scaling Law). τ is a circuit's time constant, the delay a signal accumulates crossing a stage of logic. The proposal is to scale τ rather than nanometer measurements. Compress delay rather than pitch, through techniques such as Huawei's LogicFolding, which lifts circuit layout off the plane and folds critical paths vertically so that long horizontal interconnects become short vertical ones. The character chosen to carry the pun, 韬 (tāo), is the one in 韬略 (tāolüè), meaning "strategy".
Huawei has already been doing this: 381 chips brought to volume production on the principle over six years. A follow-up paper posted to ChinaXiv in July 2026, Tau Law V2, adds production data of Huawei's own measuring. The Kirin 2026 is the first chip built on LogicFolding and expected to arrive with the Mate 90 series. Huawei puts it at 238 million transistors per square millimeter (MTr/mm²) against 155 MTr/mm² for its planar predecessor on the same process node, a 55% step, with a 41% gain in power efficiency. SemiAnalysis, measuring the process rather than the product, puts SMIC's N+3 library density at 113.4 MTr/mm²; TechInsights puts it below 125 MTr/mm². Huawei's stated ambition is 1.4-nm-equivalent density by 2031, without frontier lithography.16 "Equivalent" is a density claim, not a printing claim.
The τ Law names something the industry has practiced since the printing limit froze. For 12 years, density climbed through exactly this kind of work, and the node names detached from the critical dimension it used to measure. The imec 2038 roadmap implicitly agrees with the premise, finding most of its remaining density in cell design and stacking rather than pitch. Huawei is not expounding something new to the industry; it is naming it. And names have power: Moore's Law did that job for 60 years, coalescing roadmaps within a sprawling industry. τ Law is built to replicate that for the Chinese domestic industry, aligning it around an optimization metric that does not only run through printable feature size. The frontier's own A14 lands near 2028, so Huawei's own stated best case sits one node and roughly three years behind, pulling every lever except the light.
Practice Lights versus Production Power
China has two scanner-class programs for making 13.5 nm light, both built on tin plasma. LPP (laser-produced plasma) is ASML's own architecture, tin droplets detonated by laser pulses; the flagship effort runs at the Shanghai Institute of Optics and Fine Mechanics (SIOM) under 林楠 (Lin Nan), who ran metrology and inspection light-source technology in ASML's research department. They're driving tin plasma with a solid-state laser rather than ASML's TRUMPF CO₂ laser, a bet on solid-state for the next generation.
LDP (laser-assisted discharge plasma) makes the light instead with an electric discharge, tin vaporised between electrodes by a trigger laser. The industry tried discharge first and gave it up for volume printing: electrodes eroding in their own plasma cap the power far below manufacturing levels, and the last program aimed at scanners closed in 2013. The technology settled into humbler work: Ushio, a Japanese light-source firm, sells a commercial tin discharge source for the mask-inspection equipment that serves EUV mass production.17 China's LDP program is the same physics, cheap, compact and available now.18 And China's LPP flagship scopes itself the same way: SIOM's paper describes its source, at current power, as suited to mask inspection and exposure verification.19
What a scanner receives is power at intermediate focus: the light actually delivered into the machine, ending where the mirrors’ toll begins. ASML's published milestones run from 1 W in 2010 to 250 W in the 2018 production tool, with trade coverage putting the current industrial source at 600 W. China's side of that comparison has no number in it. No Chinese group has published a measured average power for a 13.5 nm source: the literature carries conversion efficiency, energy per pulse and peak power, and stops there. The watt figures in circulation are simulations and design targets.
Conversion efficiency, the share of drive energy that becomes usable 13.5 nm light, is where the gap is narrowest: SIOM published 3.42% in 2025 on a solid tin target, against roughly 5.5% for a commercial source. The plasma physics is broadly in hand; what is missing is the industrial machinery around it: the 30 kW drive laser, a collector that survives months of tin, dose control at production rates.
A lithography machine is one line in a long bill of materials: resists that respond to 13.5 nm photons, masks and pellicles that survive them, mirrors and the interferometers that certify them, metrology to measure what was printed, eventually a domestic scanner around it all. Each has to be developed and qualified against actual EUV light, and China cannot buy time on anyone else's. Before the printer, then, comes a light to practice against: far too weak to manufacture anything, bright enough to expose a resist sample, inspect a mask, calibrate an instrument. The industry's word for it is a bench; call it a practice light. The watt-level sources behind the "China has EUV" headlines are practice lights; Lin Nan's own ASML career was spent on exactly this class of source. The sequence is deliberate: qualify the resists, the masks and the instruments first, and build the machine into an ecosystem that is ready for it.
In October 2025 China's standards administration publicized the project for its first national test-methods standard for EUV photoresists, proposed by a university, a national laboratory, a fab, and SMEE, the lithography-machine maker whose most advanced logic tool is rated at 90 nm.20 The plan has since advanced to public comment under a reshuffled drafting group: chemistry and EUV-systems specialists in, the fab and the toolmaker out. The chemistry involved, the tin-based metal-oxide resist class the frontier itself needs for High-NA, is in the open literature and the patent files. Standards bodies write test methods when there is something arriving to test.21
The resist standard is one item on a longer list: multilayer mirror coatings published for 13.5 nm and below, a steady output of interferometry and surface-metrology work, the practice lights themselves. They are building all of it before they have the machine, presumably because they expect EUV in their near future.
On the other side of this gap, ASML has already demonstrated power production at 1,000 W, behind optics only Zeiss has ever coated at this scale, with a head start approaching 30 years that is still widening. Reasonable people can argue whether the distance is 10 years or 20 but on the tin-plasma path, the distance is growing, not shrinking.
Watts alone would not close it either. A source that reaches 100 W is not one-sixth of a production source, because the decade ASML spent between working prototype and volume manufacturing went mostly into the unglamorous remainder: wafers per hour, source availability, collector lifetime, dose stability across a shift. A tool that runs 30% of the time does not print 30% of the wafers: below a threshold of reliability, a fab cannot schedule production on it at all.
Sovereignty at a markup
The gap, meanwhile, is paid for in wafers. Christophe Fouquet, ASML's chief executive, told shareholders in 2024 that substituting DUV for EUV grows less efficient with every node until it becomes prohibitively expensive; he has put the lag the EUV ban imposes on China's manufacturing at 10 to 15 years. On ASML's July 2026 earnings call he added that rising lithography intensity in memory partly reflects customers replacing multi-patterning with single-exposure EUV, because EUV is now the cheaper way to print.22 The first two are the seller of the machine describing what its absence costs. The third is what his customers do with their own money: where both tools are available and the pitch is tight enough, multi-patterning loses on price. The gap functions as a tax rather than a wall, levied per layer, rising per node.
A layer that EUV prints in one pass takes several on DUV. Mask counts across a node rise by ~40%, a wafer spends 1.5–2× as long under an immersion scanner, cycle time lengthens, and every added step is another chance to lose the wafer.23 A chip printed two nodes behind also burns roughly twice the electricity for the same compute, charged for the life of the part.24
China is not choosing between the two tools; it is cut off from the Twinscan. The alternative is not printing these nodes at all, and against that the tax is cheap.25 What it costs is competitiveness, not capability.
The US is still widening the pressure campaign. What began in 2023 as a license requirement on ASML's most advanced immersion machines now reaches the spare parts, software and servicing for the tools already installed, and legislation before the US Congress would extend it to every immersion sale; a fleet that cannot be serviced shrinks by itself. China's answer arrived in July 2026, a domestic immersion scanner with five units planned this year against the roughly 130 ASML ships, which does nothing about EUV and everything about the servicing clause.26
The (obvious) consequences of technology sanctions
Most of what the industry's own roadmap requires is what China has already been building because it was forced to: the materials, the stacking, the packaging, the backside power, the folded logic. In some of it China is at the frontier; most of the rest is closing at ordinary commercial speed. A domestic 0.33 NA scanner, if the LPP program eventually feeds one, would not advance the world's frontier at all, and would advance China's enormously, unlocking at home the 7-, 5- and 3-nm classes the rest of the world printed on exactly that lens. Even a program that never catches ASML pays for itself along the way: every bench hour qualifies a resist, certifies an interferometer, matures a tool, trains a supply chain that already sells at the trailing edge.
Chasing the Twinscan means chasing a machine ASML and Zeiss are still improving, behind 30 years of accumulated knowledge and with their largest customers funding the next increment. China will keep chasing, and should: a domestic source in the tens of watts would run no production line, but it would qualify everything that has to be ready before one exists. Reach 50–100 W with the reliability to match, and a fab could spend EUV where multi-patterning costs most, on a handful of critical layers. That is a long stride for Chinese chips and still not the frontier.
The gap, the convergence and the compounding are all in the public record at once, which is why both headline narratives fail. "20 years behind" ignores that most of the game no longer runs through the EUV light. "Secret breakthrough" ignores that the machine is the one place a secret is impossible: the light is counted in watts and the optics in picometers, and both are published. There is no visible path to catching the ASML EUV light machine, produced by the dozens each year, crated up and shipped everywhere the US allows.
But nothing says the light has to arrive in a crate. 光刻机 (guāngkèjī) is the lithography machine; 光刻工厂 (guāngkè gōngchǎng) is the lithography factory, a term in circulation in China for something that never crosses a border: infrastructure that makes EUV light where it stands. The judgment behind it is not new: the tin plasma’s ceiling has been on the Chinese record since 2020.27 Whether 13.5 nm photons can reach a wafer without vaporizing tin has a public record too, thinner and stranger. It is a question for After Dark, where things are no longer in plain sight.
Derivations
E1 · The imec roadmap, in detail
PNode set and anchors from the imec 2026 roadmap edition, as published June 2026: A14 near 2028; contacted poly pitch stops at A10 in 2030, at 42 nm; A3-class at 2038. High-NA (0.55) is inserted at A14 and held four nodes; the 0.75 aperture appears only as a hedge, and no such lens exists.
PDevice row: nanosheet through A10, CFET from A7 with forksheet surviving as an optional bridge, sequential-to-bonded CFET at A3. Backside power delivery optional through A10, mandatory with CFET from A7. Cell heights ~115 → ~80 → ~64 → 50 nm; CPP ~45 → 42 (stop) → 39 nm.
PNode years follow Tom’s Hardware’s reporting of the 2026 edition, 29 June 2026: A14 2028, A10 2030–31, A7 2033, A5 2035–36, A3 2038. TrendForce’s later summary is derivative and carries no A7 year.
!Two items are source-dependent. Reports place bonded CFET at A3 (Tom’s Hardware) or at A5 (TrendForce), and imec’s own material gives no year. The 0.75 aperture is ASML’s roadmap figure, held in feasibility study rather than committed; imec names a hyper-NA requirement for A3 without naming a number.
ANode names are labels, not printed dimensions; Exhibit 1 shows the divergence.
!Insertion of the 0.55 lens at A14 is the roadmap’s, not the industry’s. Intel has committed to High-NA for 14A in 2027–28, and Samsung and SK hynix have installed tools; TSMC is reported to have decided against High-NA for its 1.4-nm node (TrendForce, 16 February 2026), which is not confirmed in a TSMC publication and is carried here as a report. Exhibit 1 dates the 0.55 step by tool insertion; Exhibit 2 and this note date A14 by imec’s node year, which is why the two exhibits carry different years for the same lens.
AThree nodes carry near-identical names – imec’s roadmap A14, TSMC’s A14 and Intel’s 14A. The A14 used throughout this essay is imec’s.
E2 · Exhibit 3, the placement of each lever
PThe receipts, lever by lever: device stacking and bonding (YMTC shipping hybrid-bonded NAND from Xtacking 2.0 in 2021, first among memory makers on patent position, behind TSMC and Adeia in the field); materials (batch 12-inch MoS₂ at Peking University, Fudan’s 5,900-transistor processor, with 300 mm integration leadership still at the imec consortium); patterning (7-nm class shipped on 193 nm light; SiCarrier’s CN117080054B removing an EUV cut mask at 5-nm-class back-end pitch); etch and deposition (AMEC verified at 5 nm by TSMC in 2018, 270+ chambers in 5-nm-and-below lines); packaging (AMIES’ company-claimed shares, minimal CoWoS-class capacity, ¥27.4bn of new capacity announced in H1 2026); the light (no measured average power in the published record). Full citations in the References below.
AThe four-step scale is qualitative. Within the frontier zone, etch sits at the low end (a frontier-verified toolmaker, not a frontier fab), patterning at the middle (shipped, at the cost the body prices), materials above it (publication leadership, with integration still elsewhere) and stacking at the top. These placements are author estimates.
AEDA is placed at the low end of “behind, closing”: domestic flows are established at mature nodes, while advanced-node sign-off still runs on Cadence, Synopsys and Siemens. The placement is an author estimate, and it is the lever on this chart least settled by public evidence.
AHybrid bonding is placed at the top of the frontier zone rather than at “leads”, and no lever on this chart occupies that step. YMTC leads all memory makers on hybrid-bonding patent position and has shipped wafer-to-wafer bonding in NAND since 2021, but it does not lead the field: Sony reached wafer-to-wafer copper-to-copper bonding in mass production first, in 2016, and Adeia owns the foundational process IP that YMTC licensed in 2021.
!Backside power delivery is placed at “behind, closing” on the strength of the open research record alone; no domestic production insertion exists to grade it against.
E3 · The immersion fleet and the servicing clause
PThe capacity ceiling is enforced in tools. ASML’s most advanced immersion machines have required Dutch export licenses since September 2023 (NXT:2000i and subsequent); since September 2024 the licenses cover spare parts, software and servicing for the restricted tools already installed (Reuters, 10 September 2024); May 2025 reporting tied SMIC’s yield troubles to maintenance it could no longer buy. A fleet that cannot be serviced shrinks by itself.
PThe MATCH Act (H.R. 8170), reported out of the House Foreign Affairs Committee on 22 April 2026, with S. 4281 as its Senate companion, would extend both instruments: a ban on all immersion DUV sales, and a servicing prohibition covering SMIC, CXMT, YMTC, Hua Hong, Huawei and their affiliates.
PThe domestic immersion scanner is built by Shanghai Aishengna, a state-backed company holding the immersion teams absorbed from SMEE and from Yuliangsheng, whose tool SMIC has been testing since September 2025: a program carved out of SMEE rather than grown inside it (Reuters, 28 July 2026; the wider restructuring, per TrendForce in January 2026, moved front-end lithography to Yuliangsheng and packaging equipment to AMIES). The reported plan is 5 units in 2026 and about 20 in 2027 (The Information, 27 July 2026), behind ASML’s tools on throughput, overlay and reliability (J.P. Morgan analysis cited by Reuters), against roughly 130 immersion systems ASML ships in a year.
PThe AI Futures Project forecast of 19 June 2026 puts commercial-scale Chinese immersion in the mid-2030s, with ASML at 98.7% of the immersion market. Five units is not commercial scale, and the two reports do not yet disagree.
AThe inference here is that the program’s value is insurance against the servicing clause, and that none of it bears on the EUV gap.
Workings 门道
Two of this essay's exhibits are maintained as standing pages, written for a reader arriving cold.
References
TechInsights, Kirin 9030 process analysis, December 2025: SMIC N+3 confirmed, a “scaled evolution” of the 7-nm class. SemiAnalysis N+3 teardown, June 2026: self-aligned quadruple patterning on fins and M0.
↩ASML’s published single-exposure limit: 40 nm on the XT:1900i, announced 11 July 2006 and shipped mid-2007; 38 nm from the XT:1950i, release of 15 July 2008, whose title calls it “the limit of single-patterning lithography.” The current NXT:2050i is still specified at 38 nm, on dipole illumination (40 nm on C-quad).
↩Intel’s 45-nm node at ≈3.3 MTr/mm² against TSMC’s N7 at ≈91 MTr/mm²: 27.4×. Vendor-published densities. The 45-nm node was printed on dry ArF; the 40 nm immersion limit applies from “32”.
↩Zeiss SMT and TRUMPF's internal figures: 50,000 tin droplets per second, each roughly a third the width of a human hair; a CO₂ amplifier chain delivering over 30 kW of mean pulse power, two pulses per droplet; plasma near 220,000 °C, some 40 times the 5,500 °C at the surface of the sun.
↩Zeiss SMT: up to 70% reflectance per Mo/Si mirror, 40–50 bilayer pairs, graded coatings. Neither Zeiss nor ASML publishes an end-to-end transmission figure, and published counts of the optical train run from 10 to 12 reflective surfaces. This essay uses 11, which is the count consistent with the commonly quoted ~2%: 0.70 through 11 surfaces gives 1.98%, through 12 gives 1.38%.
↩Intel press release, 11 September 1997: the EUV LLC “will invest $250 million in private funding over the next three years” – “the largest investment ever by private industry in a Department of Energy research project.” That is the founding pledge, not the programme total; the consortium grew (Infineon and Micron in May 2000, IBM in March 2001) and ran to about 2003. CSET, “Tracing the Emergence of Extreme Ultraviolet Lithography,” July 2024: Intel to pay 100% of the labs’ EUV research costs under the CRADA; ~$1 billion of separate DARPA lithography funding, 1991–2005.
Nikon’s EUV1 full-field tool and its planned successors: EE Times, 2007–2010. Neither Nikon nor Canon announced an exit; the dates here are last public activity – Canon at SPIE in 2009, Nikon at the EUVL Symposium in October 2011. SVG was the last American maker of leading-edge projection scanners; Ultratech continued to build steppers until Veeco acquired it in 2017.
↩ASML Customer Co-Investment Program: SEC Form 6-K exhibits, July–October 2012. 23% aggregate stake, €3.85bn; €1.38bn of R&D commitments, of which the larger share was 450 mm wafer development rather than lithography – €553m of Intel’s €829m, against €276m for EUV.
↩ASML publishes no source-power specification for the NXE:3800E or the EXE tools; it publishes throughput. Its own 2025 annual report gives the power history as 1 W in 2010, 250 W in 2018 at 125 wph, a 500 W prototype in 2022 and a first-ever 1,000 W in April 2025, presented at SPIE Advanced Lithography in February 2026. The 600 W figure for the current industrial source is trade coverage (Bits&Chips, February 2026); NIST SP 1500-208 (2023) describes 600 W as a laboratory demonstration against 250 W in commercial tools. Next generation: 1,000 W, 100,000 droplets per second, three pulses each, production tools targeted around 2030 (Reuters / Tom’s Hardware, 24 February 2026).
↩imec 2026 roadmap edition. Node years and pitches are Tom’s Hardware’s 29 June 2026 reporting: A14 near 2028, A10 at 2030–31 with contacted poly pitch stalling at 42 nm, A7 at 2033, A5 at 2035–36, A3 at 2038 with CPP resuming at 39 nm. Nanosheet through A10, CFET a production candidate from A7, with imec’s outer-wall forksheet described as extending the nanosheet era to A10. High-NA inserted at A14. The node-by-node detail is Derivation E1.
↩YMTC announced Xtacking at the Flash Memory Summit in August 2018 and had 64-layer parts in volume by September 2019, joined by billions of metal vias; the first teardown-confirmed copper-to-copper hybrid bond is the 128-layer Xtacking 2.0, shipping from around September 2021 (TechInsights). YMTC licensed Xperi’s DBI hybrid bonding in October 2021.
Wafer-to-wafer hybrid bonding reached mass production first at Sony, in the IMX260 of 2016, and Kioxia has shipped it in NAND since 2023. KnowMade’s patent landscape ranks the field TSMC, then Adeia/Xperi, then YMTC, then Intel; YMTC’s 119 hybrid-bonding patents lead all memory makers, against Samsung’s 83 and SK hynix’s 11. Samsung licensing YMTC patents from its tenth-generation NAND is a single-outlet report (ZDNet Korea, 13 February 2025) on unnamed sources, never confirmed by Samsung.
↩Peking University (Liu Kaihui group): batch growth of monolayer MoS₂ to 12-inch wafers, 2023. Fudan (Zhou Peng / Bao Wenzhong): “WUJI,” a 32-bit RISC-V microprocessor of 5,900 MoS₂ transistors, Nature, April 2025; a first wafer-scale 2D FPGA of ~4,000 transistors, National Science Review, online 31 October 2025.
↩SiCarrier patent CN117080054B, assignee 深圳新凯来, filed 22 September 2023, granted 15 December 2023 (Google Patents). Claim 1 recites a self-aligned truncation scheme in which a thicker sidewall film forms the cut pattern without a separate aligned exposure; no claim recites a node or a pitch. The 5-nm language is in the detailed description and is scoped to 后道 – back-end wiring – with a stated capability of 28–40 nm BEOL pitch on 193 nm immersion plus SAQP. Bloomberg’s March 2024 report was correspondingly hedged.
↩AMEC 5-nm etch verified by TSMC: DigiTimes, December 2018, company-announced; >270 AMEC CCP chambers in ≤5-nm lines globally per 2024 disclosures. NAURA holds more than 60% of the oxidation-furnace segment of SMIC’s 28-nm lines, per Chinese trade press (EEFocus, February 2026) rather than a company disclosure.
↩First domestic TC-bonder in CoWoS-L test sampling, August 2025 (company release).
The ¥27bn is announcements, not spending: ¥27.42bn of expansion projects and fundraising disclosed by JCET, Forehope, Tongfu and Huatian during the first half of 2026 (经济观察报, 12 July 2026). JCET’s Lingang project is ¥7.8bn with phase 1 completing in the second half of 2028; Forehope’s ¥12.4bn includes a phase-3 build scheduled over 96 months; Tongfu’s ¥4.22bn is a private-placement ceiling rather than a project spend; Huatian’s is ¥3.0bn. Actual first-half capital expenditure across the four is roughly half the headline – JCET’s full-year 2026 fixed-asset budget is about ¥10bn and Tongfu’s plan ¥9.1bn. TrendForce’s 29 July 2026 survey is a different basket: about ten projects announced May to July, nearing ¥40bn, including unlisted firms and omitting Tongfu.
↩AMIES market shares are the company’s own claims (TrendForce / SCMP, October–November 2025): roughly 90% domestic and ~35% global, in packaging lithography.
↩Huawei, “New Semiconductor Path in Practice,” He Tingbo keynote, IEEE ISCAS, Shanghai International Convention Center, 25 May 2026. He Tingbo et al., “A Time Scaling Theory for Multi-Layer Electronic Systems” (多层电子系统的时间缩微理论), ChinaXiv 202605.00224. Huawei’s figures: Kirin 2026 at 238 MTr/mm² against 155 for the Kirin 9030 Pro, stated by Huawei as a 55% step (155 to 238 is 53.6%); a 41% power-efficiency gain, which at fixed performance is a power reduction of roughly a third, not 41%; 381 chips brought to volume production between May 2020 and May 2026. The paper’s own 2031 endpoint is 400+ MTr/mm²; the 1.4-nm-equivalent framing is from Huawei’s press release. Mate 90 timing is trade press (TrendForce, August 2026), not a Huawei announcement.
The two density figures are not measured on the same thing. SemiAnalysis’s 113.4 MTr/mm² (14 June 2026) is a Bohr-metric library density for the SMIC N+3 process – 60% NAND2 gate area, 40% scan flip-flop, from a measured 228 nm cell height, 57 nm contacted gate pitch and 32.5 nm M0 pitch – and it publishes no die density for the Kirin 9030 Pro. TechInsights independently puts N+3 below 125 MTr/mm². Huawei’s 155 is a product figure on an undisclosed basis, and it sits above both process ceilings; the paper notes a 68% area utilization for Kirin SoC designs, and 155 × 0.68 = 105, which would land under the library figure. No published source states the reconciliation. SemiAnalysis’s remark about density measured per stacked-package footprint is directed at Huawei’s 2030–31 projections, not at this baseline.
↩Ushio Inc., July 2019 release: first acceptance of a tin LDP EUV source into mask-inspection equipment serving EUV mass production; TinPhoenix brand, September 2019.
↩China’s published LDP work runs through Harbin Institute of Technology, with discharge-source and collector papers in the open literature since the early 2010s; the programme’s 13.5 nm source took first prize in a Heilongjiang provincial innovation competition in December 2024.
Reuters’ investigation of 17 December 2025 reports, on two anonymous sources, a Shenzhen laboratory that completed a laser-produced-plasma prototype in early 2025 which generates EUV light but has not produced working chips, with Beijing targeting 2028 and the sources calling 2030 more realistic. Reuters states no power figure. The “around 100 W” in circulation is Asia Times, 18 December 2025, attributed to Chinese media and describing the Harbin discharge work as a separate, parallel line.
↩Lin Nan team, SIOM: solid-state-driven LPP-EUV at 3.42% conversion efficiency, measured on a solid tin target rather than droplets, Chinese Journal of Lasers (中国激光), Vol. 52 No. 6, March 2025, cover article. The same paper gives commercial CO₂-driven conversion efficiency as 5.5% and scopes its own watt-level output to exposure verification and mask inspection. Lin Nan’s ASML role per SIOM’s own biography: R&D scientist in the Research department and head of its metrology and inspection light-source technology.
For comparison among solid-state drivers, ARCNL reported 5.0% with a 2 µm-driven tin microdroplet plasma in December 2023, a figure the same group has since restated as about 4%; Gigaphoton published 5.2% peak with a CO₂ main pulse in 2012.
↩SMEE’s 600-series rated at 90 nm: TrendForce, November 2025. The AI Futures Project forecast finds the SSA600 prototyped in 2011 with no sustained commercial sales; only SMEE’s older i-line tools have shipped in volume.
↩National plan 20256881-T-469 under TC203, publicized 23 October 2025. Proposers: Shanghai University, Zhangjiang Laboratory, Shanghai Huali, SMEE.
The public-comment draft lists a reshuffled group per the current SAMR plan page – added: Suzhou Laboratory, Shanghai IC Materials Research Institute, Dalian University of Technology, Huarui Xincai (resists) and Dishui Weiguang (EUV lithography systems); dropped: Huali and SMEE.
↩C. Fouquet: ASML annual shareholders’ meeting, 2024 (DUV-for-EUV substitution economics); NRC interview, December 2024 (the EUV ban puts China’s chipmaking 10 to 15 years behind); ASML Q2 2026 earnings call (memory customers replacing multi-patterning with single-exposure EUV; R. Dassen: ~130 immersion systems in 2026, +30% immersion capacity planned for 2027).
↩Mask count: TSMC’s IEDM 2019 chart is normalized to N16, showing N5 at 1.35× with EUV against 1.91× without – a ratio of about 1.42×. The absolute counts in circulation (81 masks against 115) are WikiChip’s back-calculation from an assumed baseline, and Scotten Jones reads the same chart differently; the ratio is the sound figure. Samsung’s own 7LPP release puts the saving at “about 20%” of total masks, while noting that a single EUV exposure can replace up to four ArF masks at a given layer. The 4× figures in this literature are per-layer at selected steps; the node-level figures are 1.3× to 2×.
Scanner hours: AEI, “The Lithography Loophole” (Fedasiuk and Torres, April 2026), estimates that Chinese fabs burn one and a half to two times the ArF-immersion scanner hours per wafer that TSMC does with EUV. The authors give no derivation; it is their estimate, not a measurement.
Self-aligned quadruple patterning costs one lithographic exposure plus two spacer deposition and etch cycles; a finished metal layer typically takes about three masks, the mandrel plus cut and block. Four exposures describes litho-etch multi-patterning, a different scheme. The pitch division carries no overlay error, which is the point of a self-aligned flow; the error budget moves instead to pitch walking and to the cut masks, which TEL has shown exceeding a 7.9 nm edge-placement budget at 30 nm pitch.
↩TSMC’s published node figures: N5 −30% power vs N7 at iso-performance; N3E >30% vs N5. Compounding: 0.70 × 0.66 ≈ 0.46, roughly half the power two nodes ahead – hence roughly twice the electricity two nodes behind.
↩On an AI accelerator the logic die is a minority of the manufacturing bill, with high-bandwidth memory the dominant line: cost-model estimates put the H100’s logic die near $300 of a roughly $3,320 build (Silicon Analysts; Epoch AI, Raymond James and TrendForce compilations). A multiple on the logic slice therefore moves the finished part by a fraction.
↩ASML statement, 1 September 2023: Dutch license requirement for the NXT:2000i and subsequent. Dutch government, September 2024: licenses required for spare parts, software and servicing of restricted installed tools (Reuters, 10 September 2024); May 2025 reporting tied SMIC’s yield troubles to maintenance it could no longer buy. The MATCH Act (H.R. 8170, Senate companion S. 4281) was ordered reported by the House Foreign Affairs Committee on 22 April 2026 in the nature of a substitute, 36–8; the immersion-sales ban and the servicing prohibition described here are the introduced text.
The domestic scanner is built by Shanghai Aishengna, holding immersion teams absorbed from SMEE and from Yuliangsheng, whose tool SMIC has been testing since September 2025 (Reuters, 28 July 2026). Five units in 2026 and about 20 in 2027 per The Information, 27 July 2026, against roughly 130 immersion systems ASML ships in a year (R. Dassen, ASML Q2 2026 earnings call). The node-by-node detail is Derivation E3.
↩Peng Li, Ming Li, Dai Wu, Zheng Zhou and Chun Tang, 我国自由电子激光技术发展战略研究 / “Development Strategy of Free Electron Laser Technology in China,” 《中国工程科学》 (Strategic Study of the Chinese Academy of Engineering) 22(3), 9 July 2020, 35–41. The authors are at the Institute of Applied Electronics, China Academy of Engineering Physics (中国工程物理研究院), Mianyang – a different institution from the Chinese Academy of Engineering, which publishes the journal.
The paper sets four directions for breakthroughs before 2035: 在2035年前着力在长波波段FEL、X射线FEL、新型FEL、基于FEL的极紫外(EUV)光刻光源等方面取得突破. On the light source it states that the industry “requires a new type of light source with power in the order of kW, which cannot be provided by the traditional laser plasma light source technology,” and prescribes a three-step course of verification, principle prototype and 产业化布局 (industrialization layout).
光刻工厂 is a term in circulation in Chinese technical discussion rather than an official designation; it does not appear in this paper.
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